fix hardware files

Looks like it didn't work in JLCPCB...

Author: NuclearPhoenixx

hardware/BOM.csv

@@ -3,7 +3,7 @@ METRIC,LZ,000.000
 ;FILE_FORMAT=3:3
 ;TYPE=NON_PLATED
 ;Layer: NPTH_Through
-;EasyEDA v6.5.44, 2024-08-29 13:08:05
+;EasyEDA v6.5.51, 2025-11-10 15:39:41
 ;16ae97f49be74552a1a67efb210d0a0d,9a5be75d700b4a6385dc1106f27949ae,10
 ;Gerber Generator version 0.2
 ;Holesize 1 = 3.400 mm

hardware/Gerber_PCB/Drill_NPTH_Through.DRL

@@ -3,7 +3,7 @@ METRIC,LZ,000.000
 ;FILE_FORMAT=3:3
 ;TYPE=PLATED
 ;Layer: PTH_Through
-;EasyEDA v6.5.44, 2024-08-29 13:08:05
+;EasyEDA v6.5.51, 2025-11-10 15:39:41
 ;16ae97f49be74552a1a67efb210d0a0d,9a5be75d700b4a6385dc1106f27949ae,10
 ;Gerber Generator version 0.2
 ;Holesize 1 = 0.310 mm

hardware/Gerber_PCB/Drill_PTH_Through.DRL

@@ -3,7 +3,7 @@ METRIC,LZ,000.000
 ;FILE_FORMAT=3:3
 ;TYPE=PLATED
 ;Layer: PTH_Through_Via
-;EasyEDA v6.5.44, 2024-08-29 13:08:05
+;EasyEDA v6.5.51, 2025-11-10 15:39:41
 ;16ae97f49be74552a1a67efb210d0a0d,9a5be75d700b4a6385dc1106f27949ae,10
 ;Gerber Generator version 0.2
 ;Holesize 1 = 0.310 mm

hardware/Gerber_PCB/Drill_PTH_Through_Via.DRL

@@ -1,5 +1,5 @@
 G04 Layer: BoardOutlineLayer*
-G04 EasyEDA v6.5.44, 2024-08-29 13:08:05*
+G04 EasyEDA v6.5.51, 2025-11-10 15:39:41*
 G04 16ae97f49be74552a1a67efb210d0a0d,9a5be75d700b4a6385dc1106f27949ae,10*
 G04 Gerber Generator version 0.2*
 G04 Scale: 100 percent, Rotated: No, Reflected: No *
@@ -10,6 +10,7 @@ G04 leading zeros omitted , absolute positions ,4 integer and 5 decimal *
 
 %ADD10C,0.2540*%
 %ADD11C,0.0254*%
+%ADD12C,0.0119*%
 D10*
 X11800027Y-4999987D02*
 G01*