Bump DiffTest: expose cpu and mem AXI4 for fpgadiff (#258)

Author: klin02

difftest

@@ -20,6 +20,7 @@ import bus.axi4._
 import chisel3._
 import device.AXI4RAM
 import difftest._
+import difftest.fpga.DifftestMemCtrl
 import nutcore.NutCoreConfig
 import system._
 
@@ -35,13 +36,14 @@ class NutShellSim extends Module with HasDiffTestInterfaces {
   soc.io.frontend <> mmio.io.dma
 
   memdelay.io.in <> soc.io.mem
-  mem.io.in <> memdelay.io.out
 
   mmio.io.rw <> soc.io.mmio
 
   soc.io.meip := mmio.io.meip
 
   override def cpuName: Option[String] = Some("NutShell")
+  val memIO = DifftestMemCtrl.exposeIO(memdelay.io.out, mem.io.in)
+  override def difftestMemIO: Option[DifftestMemIO] = Some(memIO)
 
   val uart = IO(new UARTIO)
   uart <> mmio.io.uart

src/main/scala/sim/NutShellSim.scala

@@ -20,7 +20,7 @@ import chisel3._
 import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage._
 import device.AXI4VGA
-import difftest.{DifftestModule, DifftestTopIO, HasDiffTestInterfaces}
+import difftest.{DifftestMemIO, DifftestModule, DifftestTopIO, HasDiffTestInterfaces}
 import nutcore.NutCoreConfig
 import sim.NutShellSim
 import system.NutShell
@@ -39,6 +39,7 @@ class Top extends Module {
 class FpgaDiffTop extends NutShell()(NutCoreConfig(FPGADifftest = true)) with HasDiffTestInterfaces {
   override def desiredName: String = "NutShell"
   override def cpuName: Option[String] = Some("NutShell")
+  override def difftestMemIO: Option[DifftestMemIO] = Some(DifftestMemIO(io.mem))
 }
 
 object TopMain extends App {
@@ -88,4 +89,4 @@ object TopMain extends App {
     :+ FirtoolOption("--disable-annotation-unknown")
     :+ FirtoolOption("--default-layer-specialization=enable")
   )
-}
+}