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arghunterarghunter
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Merge pull request #3 from MIT-OpenCompute/optimize-decoder
Optimize instructions - 400 LUT Reduction
2 parents b15d18f + ba4b93f commit e2a46cd

28 files changed

Lines changed: 492 additions & 1036 deletions

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‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,8 @@
5353
// Output Output Phase Duty Cycle Pk-to-Pk Phase
5454
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
5555
//----------------------------------------------------------------------------
56-
// clk_out1__25.00000______0.000______50.0______181.828____104.359
56+
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
57+
// clk_out2__100.00000______0.000______50.0______130.958_____98.575
5758
//
5859
//----------------------------------------------------------------------------
5960
// Input Clock Freq (MHz) Input Jitter (UI)
@@ -62,12 +63,13 @@
6263

6364
`timescale 1ps/1ps
6465

65-
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
66+
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
6667

6768
module clk_wiz_0
6869
(
6970
// Clock out ports
7071
output clk_out1,
72+
output clk_out2,
7173
// Status and control signals
7274
input reset,
7375
output locked,
@@ -79,6 +81,7 @@ module clk_wiz_0
7981
(
8082
// Clock out ports
8183
.clk_out1(clk_out1),
84+
.clk_out2(clk_out2),
8285
// Status and control signals
8386
.reset(reset),
8487
.locked(locked),

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,8 @@
5252
// Output Output Phase Duty Cycle Pk-to-Pk Phase
5353
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
5454
//----------------------------------------------------------------------------
55-
// clk_out1__25.00000______0.000______50.0______181.828____104.359
55+
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
56+
// clk_out2__100.00000______0.000______50.0______130.958_____98.575
5657
//
5758
//----------------------------------------------------------------------------
5859
// Input Clock Freq (MHz) Input Jitter (UI)
@@ -69,6 +70,7 @@
6970
(
7071
// Clock out ports
7172
.clk_out1(clk_out1), // output clk_out1
73+
.clk_out2(clk_out2), // output clk_out2
7274
// Status and control signals
7375
.reset(reset), // input reset
7476
.locked(locked), // output locked

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml‎

Lines changed: 147 additions & 44 deletions
Large diffs are not rendered by default.

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v‎

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,8 @@
5353
// Output Output Phase Duty Cycle Pk-to-Pk Phase
5454
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
5555
//----------------------------------------------------------------------------
56-
// clk_out1__25.00000______0.000______50.0______181.828____104.359
56+
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
57+
// clk_out2__100.00000______0.000______50.0______130.958_____98.575
5758
//
5859
//----------------------------------------------------------------------------
5960
// Input Clock Freq (MHz) Input Jitter (UI)
@@ -67,6 +68,7 @@ module clk_wiz_0_clk_wiz
6768
(// Clock in ports
6869
// Clock out ports
6970
output clk_out1,
71+
output clk_out2,
7072
// Status and control signals
7173
input reset,
7274
output locked,
@@ -107,7 +109,6 @@ wire clk_in2_clk_wiz_0;
107109
wire clkfbout_buf_clk_wiz_0;
108110
wire clkfboutb_unused;
109111
wire clkout0b_unused;
110-
wire clkout1_unused;
111112
wire clkout1b_unused;
112113
wire clkout2_unused;
113114
wire clkout2b_unused;
@@ -126,13 +127,17 @@ wire clk_in2_clk_wiz_0;
126127
.COMPENSATION ("ZHOLD"),
127128
.STARTUP_WAIT ("FALSE"),
128129
.DIVCLK_DIVIDE (1),
129-
.CLKFBOUT_MULT_F (9.125),
130+
.CLKFBOUT_MULT_F (10.000),
130131
.CLKFBOUT_PHASE (0.000),
131132
.CLKFBOUT_USE_FINE_PS ("FALSE"),
132-
.CLKOUT0_DIVIDE_F (36.500),
133+
.CLKOUT0_DIVIDE_F (40.000),
133134
.CLKOUT0_PHASE (0.000),
134135
.CLKOUT0_DUTY_CYCLE (0.500),
135136
.CLKOUT0_USE_FINE_PS ("FALSE"),
137+
.CLKOUT1_DIVIDE (10),
138+
.CLKOUT1_PHASE (0.000),
139+
.CLKOUT1_DUTY_CYCLE (0.500),
140+
.CLKOUT1_USE_FINE_PS ("FALSE"),
136141
.CLKIN1_PERIOD (10.000))
137142
mmcm_adv_inst
138143
// Output clocks
@@ -141,7 +146,7 @@ wire clk_in2_clk_wiz_0;
141146
.CLKFBOUTB (clkfboutb_unused),
142147
.CLKOUT0 (clk_out1_clk_wiz_0),
143148
.CLKOUT0B (clkout0b_unused),
144-
.CLKOUT1 (clkout1_unused),
149+
.CLKOUT1 (clk_out2_clk_wiz_0),
145150
.CLKOUT1B (clkout1b_unused),
146151
.CLKOUT2 (clkout2_unused),
147152
.CLKOUT2B (clkout2b_unused),
@@ -197,6 +202,10 @@ wire clk_in2_clk_wiz_0;
197202
.I (clk_out1_clk_wiz_0));
198203

199204

205+
BUFG clkout2_buf
206+
(.O (clk_out2),
207+
.I (clk_out2_clk_wiz_0));
208+
200209

201210

202211
endmodule

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v‎

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
33
// --------------------------------------------------------------------------------
44
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
5-
// Date : Wed Mar 11 16:44:32 2026
5+
// Date : Fri Mar 13 01:23:39 2026
66
// Host : arya running 64-bit EndeavourOS Linux
77
// Command : write_verilog -force -mode funcsim
88
// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
@@ -16,32 +16,38 @@
1616
(* NotValidForBitStream *)
1717
module clk_wiz_0
1818
(clk_out1,
19+
clk_out2,
1920
reset,
2021
locked,
2122
clk_in1);
2223
output clk_out1;
24+
output clk_out2;
2325
input reset;
2426
output locked;
2527
input clk_in1;
2628

2729
(* IBUF_LOW_PWR *) wire clk_in1;
2830
wire clk_out1;
31+
wire clk_out2;
2932
wire locked;
3033
wire reset;
3134

3235
clk_wiz_0_clk_wiz inst
3336
(.clk_in1(clk_in1),
3437
.clk_out1(clk_out1),
38+
.clk_out2(clk_out2),
3539
.locked(locked),
3640
.reset(reset));
3741
endmodule
3842

3943
module clk_wiz_0_clk_wiz
4044
(clk_out1,
45+
clk_out2,
4146
reset,
4247
locked,
4348
clk_in1);
4449
output clk_out1;
50+
output clk_out2;
4551
input reset;
4652
output locked;
4753
input clk_in1;
@@ -50,6 +56,8 @@ module clk_wiz_0_clk_wiz
5056
wire clk_in1_clk_wiz_0;
5157
wire clk_out1;
5258
wire clk_out1_clk_wiz_0;
59+
wire clk_out2;
60+
wire clk_out2_clk_wiz_0;
5361
wire clkfbout_buf_clk_wiz_0;
5462
wire clkfbout_clk_wiz_0;
5563
wire locked;
@@ -58,7 +66,6 @@ module clk_wiz_0_clk_wiz
5866
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
5967
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
6068
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
61-
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
6269
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
6370
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
6471
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
@@ -89,18 +96,22 @@ module clk_wiz_0_clk_wiz
8996
(.I(clk_out1_clk_wiz_0),
9097
.O(clk_out1));
9198
(* BOX_TYPE = "PRIMITIVE" *)
99+
BUFG clkout2_buf
100+
(.I(clk_out2_clk_wiz_0),
101+
.O(clk_out2));
102+
(* BOX_TYPE = "PRIMITIVE" *)
92103
MMCME2_ADV #(
93104
.BANDWIDTH("OPTIMIZED"),
94-
.CLKFBOUT_MULT_F(9.125000),
105+
.CLKFBOUT_MULT_F(10.000000),
95106
.CLKFBOUT_PHASE(0.000000),
96107
.CLKFBOUT_USE_FINE_PS("FALSE"),
97108
.CLKIN1_PERIOD(10.000000),
98109
.CLKIN2_PERIOD(0.000000),
99-
.CLKOUT0_DIVIDE_F(36.500000),
110+
.CLKOUT0_DIVIDE_F(40.000000),
100111
.CLKOUT0_DUTY_CYCLE(0.500000),
101112
.CLKOUT0_PHASE(0.000000),
102113
.CLKOUT0_USE_FINE_PS("FALSE"),
103-
.CLKOUT1_DIVIDE(1),
114+
.CLKOUT1_DIVIDE(10),
104115
.CLKOUT1_DUTY_CYCLE(0.500000),
105116
.CLKOUT1_PHASE(0.000000),
106117
.CLKOUT1_USE_FINE_PS("FALSE"),
@@ -149,7 +160,7 @@ module clk_wiz_0_clk_wiz
149160
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
150161
.CLKOUT0(clk_out1_clk_wiz_0),
151162
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
152-
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
163+
.CLKOUT1(clk_out2_clk_wiz_0),
153164
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
154165
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
155166
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl‎

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
33
-- --------------------------------------------------------------------------------
44
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
5-
-- Date : Wed Mar 11 16:44:32 2026
5+
-- Date : Fri Mar 13 01:23:39 2026
66
-- Host : arya running 64-bit EndeavourOS Linux
77
-- Command : write_vhdl -force -mode funcsim
88
-- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
@@ -18,6 +18,7 @@ use UNISIM.VCOMPONENTS.ALL;
1818
entity clk_wiz_0_clk_wiz is
1919
port (
2020
clk_out1 : out STD_LOGIC;
21+
clk_out2 : out STD_LOGIC;
2122
reset : in STD_LOGIC;
2223
locked : out STD_LOGIC;
2324
clk_in1 : in STD_LOGIC
@@ -27,13 +28,13 @@ end clk_wiz_0_clk_wiz;
2728
architecture STRUCTURE of clk_wiz_0_clk_wiz is
2829
signal clk_in1_clk_wiz_0 : STD_LOGIC;
2930
signal clk_out1_clk_wiz_0 : STD_LOGIC;
31+
signal clk_out2_clk_wiz_0 : STD_LOGIC;
3032
signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
3133
signal clkfbout_clk_wiz_0 : STD_LOGIC;
3234
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
3335
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
3436
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
3537
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
36-
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
3738
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
3839
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
3940
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
@@ -55,6 +56,7 @@ architecture STRUCTURE of clk_wiz_0_clk_wiz is
5556
attribute IFD_DELAY_VALUE : string;
5657
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
5758
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
59+
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
5860
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
5961
begin
6062
clkf_buf: unisim.vcomponents.BUFG
@@ -75,19 +77,24 @@ clkout1_buf: unisim.vcomponents.BUFG
7577
I => clk_out1_clk_wiz_0,
7678
O => clk_out1
7779
);
80+
clkout2_buf: unisim.vcomponents.BUFG
81+
port map (
82+
I => clk_out2_clk_wiz_0,
83+
O => clk_out2
84+
);
7885
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
7986
generic map(
8087
BANDWIDTH => "OPTIMIZED",
81-
CLKFBOUT_MULT_F => 9.125000,
88+
CLKFBOUT_MULT_F => 10.000000,
8289
CLKFBOUT_PHASE => 0.000000,
8390
CLKFBOUT_USE_FINE_PS => false,
8491
CLKIN1_PERIOD => 10.000000,
8592
CLKIN2_PERIOD => 0.000000,
86-
CLKOUT0_DIVIDE_F => 36.500000,
93+
CLKOUT0_DIVIDE_F => 40.000000,
8794
CLKOUT0_DUTY_CYCLE => 0.500000,
8895
CLKOUT0_PHASE => 0.000000,
8996
CLKOUT0_USE_FINE_PS => false,
90-
CLKOUT1_DIVIDE => 1,
97+
CLKOUT1_DIVIDE => 10,
9198
CLKOUT1_DUTY_CYCLE => 0.500000,
9299
CLKOUT1_PHASE => 0.000000,
93100
CLKOUT1_USE_FINE_PS => false,
@@ -137,7 +144,7 @@ mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
137144
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
138145
CLKOUT0 => clk_out1_clk_wiz_0,
139146
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
140-
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
147+
CLKOUT1 => clk_out2_clk_wiz_0,
141148
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
142149
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
143150
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
@@ -169,6 +176,7 @@ use UNISIM.VCOMPONENTS.ALL;
169176
entity clk_wiz_0 is
170177
port (
171178
clk_out1 : out STD_LOGIC;
179+
clk_out2 : out STD_LOGIC;
172180
reset : in STD_LOGIC;
173181
locked : out STD_LOGIC;
174182
clk_in1 : in STD_LOGIC
@@ -183,6 +191,7 @@ inst: entity work.clk_wiz_0_clk_wiz
183191
port map (
184192
clk_in1 => clk_in1,
185193
clk_out1 => clk_out1,
194+
clk_out2 => clk_out2,
186195
locked => locked,
187196
reset => reset
188197
);

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
33
// --------------------------------------------------------------------------------
44
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
5-
// Date : Wed Mar 11 16:44:32 2026
5+
// Date : Fri Mar 13 01:23:39 2026
66
// Host : arya running 64-bit EndeavourOS Linux
77
// Command : write_verilog -force -mode synth_stub
88
// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
@@ -14,11 +14,13 @@
1414
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
1515
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
1616
// Please paste the declaration into a Verilog source file or add the file as an additional source.
17-
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
18-
module clk_wiz_0(clk_out1, reset, locked, clk_in1)
17+
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
18+
module clk_wiz_0(clk_out1, clk_out2, reset, locked, clk_in1)
1919
/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
20-
/* synthesis syn_force_seq_prim="clk_out1" */;
20+
/* synthesis syn_force_seq_prim="clk_out1" */
21+
/* synthesis syn_force_seq_prim="clk_out2" */;
2122
output clk_out1 /* synthesis syn_isclock = 1 */;
23+
output clk_out2 /* synthesis syn_isclock = 1 */;
2224
input reset;
2325
output locked;
2426
input clk_in1;

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
33
-- --------------------------------------------------------------------------------
44
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
5-
-- Date : Wed Mar 11 16:44:32 2026
5+
-- Date : Fri Mar 13 01:23:39 2026
66
-- Host : arya running 64-bit EndeavourOS Linux
77
-- Command : write_vhdl -force -mode synth_stub
88
-- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
@@ -16,19 +16,20 @@ use IEEE.STD_LOGIC_1164.ALL;
1616
entity clk_wiz_0 is
1717
Port (
1818
clk_out1 : out STD_LOGIC;
19+
clk_out2 : out STD_LOGIC;
1920
reset : in STD_LOGIC;
2021
locked : out STD_LOGIC;
2122
clk_in1 : in STD_LOGIC
2223
);
2324

2425
attribute CORE_GENERATION_INFO : string;
25-
attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
26+
attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
2627
end clk_wiz_0;
2728

2829
architecture stub of clk_wiz_0 is
2930
attribute syn_black_box : boolean;
3031
attribute black_box_pad_pin : string;
3132
attribute syn_black_box of stub : architecture is true;
32-
attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
33+
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,reset,locked,clk_in1";
3334
begin
3435
end;

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,8 @@
5252
// Output Output Phase Duty Cycle Pk-to-Pk Phase
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// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
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//----------------------------------------------------------------------------
55-
// clk_out1__25.00000______0.000______50.0______181.828____104.359
55+
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
56+
// clk_out2__100.00000______0.000______50.0______130.958_____98.575
5657
//
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//----------------------------------------------------------------------------
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// Input Clock Freq (MHz) Input Jitter (UI)
@@ -69,6 +70,7 @@
6970
(
7071
// Clock out ports
7172
.clk_out1(clk_out1), // output clk_out1
73+
.clk_out2(clk_out2), // output clk_out2
7274
// Status and control signals
7375
.reset(reset), // input reset
7476
.locked(locked), // output locked

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