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faV3Lib.c
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8691 lines (7165 loc) · 199 KB
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/**
* @copyright Copyright 2024, Jefferson Science Associates, LLC.
* Subject to the terms in the LICENSE file found in the
* top-level directory.
*
* @author Bryan Moffit
* moffit@jlab.org Jefferson Lab, MS-12B3
* Phone: (757) 269-5660 12000 Jefferson Ave.
* Newport News, VA 23606
*
* @author David Abbott
* abbottd@jlab.org Jefferson Lab, MS-12B3
* Phone: (757) 269-7190 12000 Jefferson Ave.
* Newport News, VA 23606
* @file faV3Lib.c
*
* @brief Library for JLAB configuration and readout of JLAB 250MHz
* FLASH ADC V3
*
*/
#ifdef VXWORKS
#include <vxWorks.h>
#else
#include <stddef.h>
#include <pthread.h>
#include "jvme.h"
#endif
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#ifdef VXWORKS
#include <logLib.h>
#include <taskLib.h>
#include <intLib.h>
#include <iv.h>
#include <semLib.h>
#include <vxLib.h>
#else
#include <unistd.h>
#endif
/* Include ADC definitions */
#include "faV3Lib.h"
#ifdef VXWORKS
#define FAV3LOCK
#define FAV3UNLOCK
#else
/* Mutex to guard flexio read/writes */
pthread_mutex_t faV3Mutex = PTHREAD_MUTEX_INITIALIZER;
#define FAV3LOCK if(pthread_mutex_lock(&faV3Mutex)<0) perror("pthread_mutex_lock");
#define FAV3UNLOCK if(pthread_mutex_unlock(&faV3Mutex)<0) perror("pthread_mutex_unlock");
#endif
/* Define external Functions */
#ifdef VXWORKS
IMPORT STATUS sysBusToLocalAdrs(int, char *, char **);
IMPORT STATUS intDisconnect(int);
IMPORT STATUS sysIntEnable(int);
IMPORT STATUS sysIntDisable(int);
IMPORT STATUS sysVmeDmaDone(int, int);
IMPORT STATUS sysVmeDmaSend(uint32_t, uint32_t, int, BOOL);
#define EIEIO __asm__ volatile ("eieio")
#define SYNC __asm__ volatile ("sync")
#endif
/* Define Interrupts variables */
BOOL faV3IntRunning = FALSE; /* running flag */
int faV3IntID = -1; /* id number of ADC generating interrupts */
LOCAL VOIDFUNCPTR faV3IntRoutine = NULL; /* user interrupt service routine */
LOCAL int faV3IntArg = 0; /* arg to user routine */
LOCAL uint32_t faV3IntLevel = FAV3_VME_INT_LEVEL; /* default VME interrupt level */
LOCAL uint32_t faV3IntVec = FAV3_VME_INT_VEC; /* default interrupt Vector */
/* Define global variables */
int nfaV3 = 0; /* Number of FAV3s in Crate */
uint32_t faV3A32Base = 0x09000000; /* Minimum VME A32 Address for use by FAV3s */
u_long faV3A32Offset = 0x08000000; /* Difference in CPU A32 Base - VME A32 Base */
u_long faV3A24Offset = 0x0; /* Difference in CPU A24 Base - VME A24 Base */
u_long faV3A16Offset = 0x0; /* Difference in CPU A16 Base - VME A16 Base */
volatile faV3_t *FAV3p[(FAV3_MAX_BOARDS + 1)]; /* pointers to FAV3 memory map */
volatile faV3sdc_t *FAV3SDCp; /* pointer to FAV3 Signal distribution card */
volatile uint32_t *FAV3pd[(FAV3_MAX_BOARDS + 1)]; /* pointers to FAV3 FIFO memory */
volatile uint32_t *FAV3pmb; /* pointer to Multblock window */
int faV3ID[FAV3_MAX_BOARDS]; /* array of slot numbers for FAV3s */
uint32_t faV3AddrList[FAV3_MAX_BOARDS]; /* array of a24 addresses for FAV3s */
int faV3FwRev[(FAV3_MAX_BOARDS + 1)][FAV3_FW_FUNCTION_MAX]; /* control+proc version numbers */
uint16_t faV3ChanDisableMask[(FAV3_MAX_BOARDS + 1)]; /* Disabled Channel Mask for each Module */
int faV3Inited = 0; /* >0 if Library has been Initialized before */
int faV3MaxSlot = 0; /* Highest Slot hold an FAV3 */
int faV3MinSlot = 0; /* Lowest Slot holding an FAV3 */
int faV3Source = 0; /* Signal source for FAV3 system control */
int faV3UseSDC = 0; /* If > 0 then Use Signal Distribution board */
int faV3SDCPassthrough = 0; /* If > 0 SDC in level translate / passthrough mode */
faV3data_t faV3_data;
int faV3BlockError = FAV3_BLOCKERROR_NO_ERROR; /* Whether (>0) or not (0) Block Transfer had an error */
#define CHECKID { \
if(id == 0) id = faV3ID[0]; \
if((id <= 0) || (id > 21) || (FAV3p[id] == NULL)) { \
printf("%s: ERROR : ADC in slot %d is not initialized \n", __func__, id); \
return ERROR; }}
const char *faV3_mode_names[FAV3_MAX_PROC_MODE+1] =
{
"NOT DEFINED", // 0
"RAW WINDOW", // 1
"NOT DEFINED",
"NOT DEFINED",
"NOT DEFINED",
"NOT DEFINED", // 5
"NOT DEFINED",
"NOT DEFINED",
"NOT DEFINED",
"PULSE PARAMETER", // 9
"RAW + PULSE PARAMETER" // 10
};
/**
* @defgroup Config Initialization/Configuration
* @defgroup SDCConfig SDC Initialization/Configuration
* @ingroup Config
* @defgroup Status Status
* @defgroup SDCStatus SDC Status
* @ingroup Status
* @defgroup Readout Data Readout
* @defgroup IntPoll Interrupt/Polling
* @defgroup Deprec Deprecated - To be removed
*/
/**
* @ingroup Config
* @brief Initialize JLAB FADC250 V3 Library.
*
* @param addr
* - A24 VME Address of the fADC250 V3
* @param addr_inc
* - Amount to increment addr to find the next fADC250 V3
* @param nadc
* - Number of times to increment
*
* @param iFlag 18 bit integer
* <pre>
* Low 6 bits - Specifies the default Signal distribution (clock,trigger)
* sources for the board (Internal, FrontPanel, VXS, VME(Soft))
* bit 0: defines Sync Reset source
* 0 VME (Software Sync-Reset)
* 1 Front Panel/VXS/P2 (Depends on Clk/Trig source selection)
* bits 3-1: defines Trigger source
* 0 0 0 VME (Software Triggers)
* 0 0 1 Front Panel Input
* 0 1 0 VXS (P0)
* 1 0 0 Internal Trigger Logic (HITSUM FPGA)
* (all others Undefined - default to VME/Software)
* bits 5-4: defines Clock Source
* 0 0 Internal 250MHz Clock
* 0 1 Front Panel
* 1 0 VXS (P0)
* 1 1 P2 Connector (Backplane)
* </pre>
*
* <pre>
* Common Modes of Operation:
* Value = 0 CLK (Int) TRIG (Soft) SYNC (Soft) (Debug/Test Mode)
* 2 CLK (Int) TRIG (FP) SYNC (Soft) (Single Board
* 3 CLK (Int) TRIG (FP) SYNC (FP) Modes)
* 0x10 CLK (FP) TRIG (Soft) SYNC (Soft)
* 0x13 CLK (FP) TRIG (FP) SYNC (FP) (VME SDC Mode)
* 0x20 CLK (VXS) TRIG (Soft) SYNC (Soft)
* 0x25 CLK (VXS) TRIG (VXS) SYNC (VXS) (VXS SD Mode)
*
*
* High 10bits - A16 Base address of FADC Signal Distribution Module
* This board can control up to 7 FADC Boards.
* Clock Source must be set to Front Panel (bit4 = 1)
*
* bit 16: Exit before board initialization
* 0 Initialize FADC (default behavior)
* 1 Skip initialization (just setup register map pointers)
*
* bit 17: Use fadcAddrList instead of addr and addr_inc
* for VME addresses.
* 0 Initialize with addr and addr_inc
* 1 Use fadcAddrList
*
* bit 18: Skip firmware check. Useful for firmware updating.
* 0 Perform firmware check
* 1 Skip firmware check
* </pre>
*
*
* @return OK, or ERROR if the address is invalid or a board is not present.
*/
int
faV3Init(uint32_t addr, uint32_t addr_inc, int nadc, int iFlag)
{
int ii, res, errFlag = 0;
int boardID = 0;
int maxSlot = 1;
int minSlot = 21;
int trigSrc = 0, clkSrc = 0, srSrc = 0;
uint32_t rdata, a32addr, a16addr = 0;
u_long laddr = 0, laddr_inc = 0;
volatile faV3_t *fa;
uint16_t sdata;
int noBoardInit = 0;
int useList = 0;
int multiBlockOnly = 0;
int vxsReadoutOnly = 0;
int useSlotNumbers=0;
uint16_t ctrl_version = 0, proc_version = 0;
/* Check if we have already Initialized boards before */
if((faV3Inited > 0) && (faV3ID[0] != 0))
{
/* Hard Reset of all FADC boards in the Crate */
for(ii = 0; ii < nfaV3; ii++)
{
vmeWrite32(&(FAV3p[faV3ID[ii]]->csr), FAV3_CSR_HARD_RESET);
}
taskDelay(5);
}
/* Check if we are to exit when pointers are setup */
noBoardInit = (iFlag & FAV3_INIT_SKIP) ? 1 : 0;
/* Check if we're initializing using a list */
useList = (iFlag & FAV3_INIT_USE_ADDRLIST) ? 1 : 0;
/* Check if we're only using token passing for readout */
multiBlockOnly = (iFlag & FAV3_INIT_MULTIBLOCK_ONLY) ? 1 : 0;
/* Check if we're reading out through the VXS (VTP) */
vxsReadoutOnly = (iFlag & FAV3_INIT_VXS_READOUT_ONLY) ? 1 : 0;
/* Use slot numbers for A32 addressing */
useSlotNumbers = (iFlag & FAV3_INIT_A32_SLOTNUMBER) ? 1 : 0;
if(useSlotNumbers)
faV3A32Base = 0;
/* Check for valid address */
if(addr == 0)
{
printf("%s: ERROR: Must specify a Bus (VME-based A24) address for FADC 0\n", __func__);
return (ERROR);
}
else if(addr > 0x00ffffff)
{ /* A24 Addressing */
printf("%s: ERROR: A32 Addressing not allowed for FADC configuration space\n", __func__);
return (ERROR);
}
else
{ /* A24 Addressing */
if(((addr_inc == 0) || (nadc == 0)) && (useList == 0))
nadc = 1; /* assume only one FADC to initialize */
/* get the FADC address */
#ifdef VXWORKS
res = sysBusToLocalAdrs(0x39, (char *) addr, (char **) &laddr);
#else
res = vmeBusToLocalAdrs(0x39, (char *) (u_long) addr, (char **) &laddr);
#endif
if(res != 0)
{
#ifdef VXWORKS
printf("%s: ERROR in sysBusToLocalAdrs(0x39,0x%x,&laddr) \n", __func__,
addr);
#else
printf("%s: ERROR in vmeBusToLocalAdrs(0x39,0x%x,&laddr) \n", __func__,
addr);
#endif
return (ERROR);
}
faV3A24Offset = laddr - addr;
}
/* Init Some Global variables */
faV3Source = iFlag & FAV3_SOURCE_MASK;
faV3Inited = nfaV3 = 0;
faV3UseSDC = 0;
memset((char *) FAV3p, 0, sizeof(FAV3p));
memset((char *) FAV3pd, 0, sizeof(FAV3pd));
FAV3pmb = NULL;
memset((char *) faV3ID, 0, sizeof(faV3ID));
memset((char *) faV3FwRev, 0, sizeof(faV3FwRev));
memset((char *) faV3ChanDisableMask, 0, sizeof(faV3ChanDisableMask));
for(ii = 0; ii < nadc; ii++)
{
if(useList == 1)
{
laddr_inc = faV3AddrList[ii] + faV3A24Offset;
}
else
{
laddr_inc = laddr + ii * addr_inc;
}
fa = (faV3_t *) laddr_inc;
/* Check if Board exists at that address */
#ifdef VXWORKS
res = vxMemProbe((char *) &(fa->version), VX_READ, 4, (char *) &rdata);
#else
res = vmeMemProbe((char *) &(fa->version), 4, (char *) &rdata);
#endif
if(res < 0)
{
#ifdef VXWORKS
printf("%s: WARN: No addressable board at addr=0x%x\n", __func__,
(uint32_t) fa);
#else
printf("%s: WARN: No addressable board at VME (Local) addr=0x%x (0x%lx)\n", __func__,
(uint32_t) (laddr_inc - faV3A24Offset), (u_long) fa);
#endif
errFlag = 1;
continue;
}
else
{
/* Check that it is an FA board */
if((rdata & FAV3_BOARD_MASK) != FAV3_BOARD_ID)
{
printf("%s: WARN: For board at 0x%lx, Invalid Board ID: 0x%x\n",
__func__, (u_long) fa - faV3A24Offset, rdata);
continue;
}
else
{
/* Check if this is board has a valid slot number */
boardID = ((vmeRead32(&(fa->intr))) & FAV3_SLOT_ID_MASK) >> 16;
if((boardID <= 0) || (boardID > 21))
{
printf(" ERROR: Board Slot ID is not in range: %d\n",
boardID);
continue;
/* return(ERROR); */
}
else
{
/* Check Control FPGA firmware version */
ctrl_version = rdata & FAV3_VERSION_MASK;
/* Check Processing FPGA firmware version */
proc_version =
(uint16_t) (vmeRead16(&fa->adc.status0) &
FAV3_ADC_VERSION_MASK);
FAV3p[boardID] = (faV3_t *) (laddr_inc);
faV3FwRev[boardID][FAV3_FW_CTRL] = ctrl_version;
faV3FwRev[boardID][FAV3_FW_PROC] = proc_version;
faV3ID[nfaV3] = boardID;
if(boardID >= maxSlot)
maxSlot = boardID;
if(boardID <= minSlot)
minSlot = boardID;
printf("Initialized FADC %2d Slot #%2d at VME (Local) address 0x%06x (0x%lx) \n",
nfaV3, faV3ID[nfaV3],
(uint32_t) (((u_long) FAV3p[(faV3ID[nfaV3])]) - faV3A24Offset),
(u_long) FAV3p[(faV3ID[nfaV3])]);
}
nfaV3++;
}
}
} // End loop through fadcs
/* Check if we are using a JLAB FADC Signal Distribution Card (SDC)
NOTE the SDC board only supports 7 FADCs - so if there are
more than 7 FADCs in the crate they can only be controlled by daisychaining
multiple SDCs together - or by using a VXS Crate with SD switch card
*/
a16addr = iFlag & FAV3_SDC_ADR_MASK;
if(a16addr)
{
#ifdef VXWORKS
res = sysBusToLocalAdrs(0x29, (char *) a16addr, (char **) &laddr);
if(res != 0)
{
printf("%s: ERROR in sysBusToLocalAdrs(0x29,0x%x,&laddr) \n", __func__,
a16addr);
return (ERROR);
}
res = vxMemProbe((char *) laddr, VX_READ, 2, (char *) &sdata);
#else
res =
vmeBusToLocalAdrs(0x29, (char *) (u_long) a16addr, (char **) &laddr);
if(res != 0)
{
printf("%s: ERROR in vmeBusToLocalAdrs(0x29,0x%x,&laddr) \n", __func__,
a16addr);
return (ERROR);
}
res = vmeMemProbe((char *) laddr, 2, (char *) &sdata);
#endif
if(res < 0)
{
printf("%s: ERROR: No addressable SDC board at addr=0x%x\n", __func__,
(uint32_t) laddr);
}
else
{
faV3A16Offset = laddr - a16addr;
FAV3SDCp = (faV3sdc_t *) laddr;
if(!noBoardInit)
vmeWrite16(&(FAV3SDCp->ctrl), FAV3SDC_CSR_INIT); /* Reset the Module */
if(nfaV3 > 7)
{
printf("WARN: A Single JLAB FADC Signal Distribution Module only supports 7 FADCs\n");
printf("WARN: You must use multiple SDCs to support more FADCs - this must be configured in hardware\n");
}
#ifdef VXWORKS
printf("Using JLAB FADC Signal Distribution Module at address 0x%x\n",
(uint32_t) FAV3SDCp);
#else
printf("Using JLAB FADC Signal Distribution Module at VME (Local) address 0x%x (0x%lx)\n",
(uint32_t) a16addr, (u_long) FAV3SDCp);
#endif
faV3UseSDC = 1;
}
if(faV3Source == FAV3_SOURCE_SDC)
{ /* Check if SDC will be used */
faV3UseSDC = 1;
printf("%s: JLAB FADC Signal Distribution Card is Assumed in Use\n", __func__);
printf("%s: Front Panel Inputs will be enabled. \n", __func__);
}
else
{
faV3UseSDC = 0;
printf("%s: JLAB FADC Signal Distribution Card will not be Used\n", __func__);
}
} // end if a16addr
/* Hard Reset of all FADC boards in the Crate */
if(!noBoardInit)
{
for(ii = 0; ii < nfaV3; ii++)
{
vmeWrite32(&(FAV3p[faV3ID[ii]]->reset), FAV3_RESET_ALL);
}
taskDelay(60);
}
/* Initialize Interrupt variables */
faV3IntID = -1;
faV3IntRunning = FALSE;
faV3IntLevel = FAV3_VME_INT_LEVEL;
faV3IntVec = FAV3_VME_INT_VEC;
faV3IntRoutine = NULL;
faV3IntArg = 0;
if(!noBoardInit)
{
/* what are the Trigger Sync Reset and Clock sources */
if(faV3Source == FAV3_SOURCE_VXS)
{
printf("%s: Enabling FADC for VXS Clock ", __func__);
clkSrc = FAV3_REF_CLK_P0;
switch (iFlag & 0xf)
{
case 0:
case 1:
printf("and Software Triggers (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_VME | FAV3_ENABLE_SOFT_TRIG;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 2:
printf("and Front Panel Triggers (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_FP_ISYNC;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 3:
printf("and Front Panel Triggers (FP Sync Reset)\n");
trigSrc = FAV3_TRIG_FP_ISYNC;
srSrc = FAV3_SRESET_FP_ISYNC;
break;
case 4:
case 6:
printf("and VXS Triggers (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_P0_ISYNC;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 5:
case 7:
printf("and VXS Triggers (VXS Sync Reset)\n");
trigSrc = FAV3_TRIG_P0_ISYNC;
srSrc = FAV3_SRESET_P0_ISYNC;
break;
case 8:
case 10:
case 12:
case 14:
printf("and Internal Trigger Logic (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_INTERNAL;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 9:
case 11:
case 13:
case 15:
printf("and Internal Trigger Logic (VXS Sync Reset)\n");
trigSrc = FAV3_TRIG_INTERNAL;
srSrc = FAV3_SRESET_FP_ISYNC;
break;
}
}
else if(faV3Source == FAV3_SOURCE_SDC)
{
printf("%s: Enabling FADC for SDC Clock (Front Panel) ", __func__);
clkSrc = FAV3_REF_CLK_FP;
switch (iFlag & 0xf)
{
case 0:
case 1:
printf("and Software Triggers (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_VME | FAV3_ENABLE_SOFT_TRIG;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 2:
case 4:
case 6:
printf("and Front Panel Triggers (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_FP_ISYNC;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 3:
case 5:
case 7:
printf("and Front Panel Triggers (FP Sync Reset)\n");
trigSrc = FAV3_TRIG_FP_ISYNC;
srSrc = FAV3_SRESET_FP_ISYNC;
break;
case 8:
case 10:
case 12:
case 14:
printf("and Internal Trigger Logic (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_INTERNAL;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 9:
case 11:
case 13:
case 15:
printf("and Internal Trigger Logic (Front Panel Sync Reset)\n");
trigSrc = FAV3_TRIG_INTERNAL;
srSrc = FAV3_SRESET_FP_ISYNC;
break;
}
faV3SDC_Config(0, 0);
}
else
{ /* Use internal Clk */
printf("%s: Enabling FADC Internal Clock, ", __func__);
clkSrc = FAV3_REF_CLK_INTERNAL;
switch (iFlag & 0xf)
{
case 0:
case 1:
printf("and Software Triggers (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_VME | FAV3_ENABLE_SOFT_TRIG;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 2:
printf("and Front Panel Triggers (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_FP_ISYNC;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 3:
printf("and Front Panel Triggers (FP Sync Reset)\n");
trigSrc = FAV3_TRIG_FP_ISYNC;
srSrc = FAV3_SRESET_FP_ISYNC;
break;
case 4:
case 6:
printf("and VXS Triggers (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_P0_ISYNC;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 5:
case 7:
printf("and VXS Triggers (VXS Sync Reset)\n");
trigSrc = FAV3_TRIG_P0_ISYNC;
srSrc = FAV3_SRESET_P0_ISYNC;
break;
case 8:
case 10:
case 12:
case 14:
printf("and Internal Trigger Logic (Soft Sync Reset)\n");
trigSrc = FAV3_TRIG_INTERNAL;
srSrc = FAV3_SRESET_VME | FAV3_ENABLE_SOFT_SRESET;
break;
case 9:
case 11:
case 13:
case 15:
printf("and Internal Trigger Logic (Front Panel Sync Reset)\n");
trigSrc = FAV3_TRIG_INTERNAL;
srSrc = FAV3_SRESET_FP_ISYNC;
break;
}
}
/* Enable Clock source - Internal Clk enabled by default */
for(ii = 0; ii < nfaV3; ii++)
{
vmeWrite32(&FAV3p[faV3ID[ii]]->ctrl1,
(clkSrc | FAV3_ENABLE_INTERNAL_CLK));
}
taskDelay(20);
/* Hard Reset FPGAs and FIFOs */
for(ii = 0; ii < nfaV3; ii++)
{
vmeWrite32(&FAV3p[faV3ID[ii]]->reset,
(FAV3_RESET_HARD_CNTL | FAV3_RESET_HARD_PROC |
FAV3_RESET_ADC_FIFO | FAV3_RESET_HITSUM_FIFO |
FAV3_RESET_DAC | FAV3_RESET_EXT_RAM_PT));
/* Release reset on MGTs */
vmeWrite32(&FAV3p[faV3ID[ii]]->ctrl_mgt, FAV3_RELEASE_MGT_RESET);
vmeWrite32(&FAV3p[faV3ID[ii]]->ctrl_mgt, FAV3_MGT_RESET);
vmeWrite32(&FAV3p[faV3ID[ii]]->ctrl_mgt, FAV3_RELEASE_MGT_RESET);
}
taskDelay(5);
}
/* Write configuration registers with default/defined Sources */
for(ii = 0; ii < nfaV3; ii++)
{
if((!multiBlockOnly) || (!vxsReadoutOnly))
{
/* Program an A32 access address for this FADC's FIFO */
if(useSlotNumbers)
a32addr = faV3ID[ii] << 23;
else
a32addr = faV3A32Base + ii * FAV3_MAX_A32_MEM;
#ifdef VXWORKS
res = sysBusToLocalAdrs(0x09, (char *) a32addr, (char **) &laddr);
#else
res = vmeBusToLocalAdrs(0x09, (char *) (u_long) a32addr, (char **) &laddr);
#endif
if ((res != 0) || (faV3A32Offset == 0))
{
FAV3pd[faV3ID[ii]] = (unsigned int *)(unsigned long) a32addr;
faV3A32Offset = 0;
}
else
{
faV3A32Offset = laddr - (unsigned long) a32addr;
FAV3pd[faV3ID[ii]] = (uint32_t *) (laddr); /* Set a pointer to the FIFO */
}
}
if(!noBoardInit)
{
/* Write a32 address and enable */
if((!multiBlockOnly) || (!vxsReadoutOnly))
vmeWrite32(&FAV3p[faV3ID[ii]]->adr32, (a32addr >> 16) + 1);
/* Set Default Block Level to 1 */
vmeWrite32(&FAV3p[faV3ID[ii]]->blocklevel, 1);
/* Setup Trigger and Sync Reset sources */
vmeWrite32(&FAV3p[faV3ID[ii]]->ctrl1,
(vmeRead32(&FAV3p[faV3ID[ii]]->ctrl1) &
~(FAV3_REF_CLK_MASK | FAV3_TRIG_MASK | FAV3_SRESET_MASK)) |
(clkSrc | srSrc | trigSrc) );
/* Initialize DAC */
faV3DACInit(faV3ID[ii]);
faV3DACClear(faV3ID[ii]);
/* Configure IDelay */
faV3LoadIdelay(faV3ID[ii], 0);
}
} //End loop through fadcs
/* If there are more than 1 FADC in the crate then setup the Muliblock Address
window. This must be the same on each board in the crate */
if((nfaV3 > 1) && (!vxsReadoutOnly))
{
if(useSlotNumbers)
a32addr = 22 << 23;
else
{
if(multiBlockOnly)
a32addr = faV3A32Base;
else
a32addr = faV3A32Base + (nfaV3 + 1) * FAV3_MAX_A32_MEM; /* set MB base above individual board base */
}
#ifdef VXWORKS
res = sysBusToLocalAdrs(0x09, (char *) a32addr, (char **) &laddr);
#else
res = vmeBusToLocalAdrs(0x09, (char *) (u_long) a32addr, (char **) &laddr);
#endif
if ((res != 0) || (faV3A32Offset == 0))
FAV3pmb = (unsigned int *)(unsigned long)a32addr;
else
FAV3pmb = (unsigned int *)(laddr); /* Set a pointer to the FIFO */
if(!noBoardInit)
{
for(ii = 0; ii < nfaV3; ii++)
{
/* Write the register and enable */
vmeWrite32(&(FAV3p[faV3ID[ii]]->adr_mb),
(a32addr + FAV3_MAX_A32MB_SIZE) + (a32addr >> 16) +
FAV3_A32_ENABLE);
}
}
/* Set First Board and Last Board */
faV3MaxSlot = maxSlot;
faV3MinSlot = minSlot;
if(!noBoardInit)
{
vmeWrite32(&(FAV3p[minSlot]->ctrl1),
vmeRead32(&(FAV3p[minSlot]->ctrl1)) | FAV3_FIRST_BOARD);
vmeWrite32(&(FAV3p[maxSlot]->ctrl1),
vmeRead32(&(FAV3p[maxSlot]->ctrl1)) | FAV3_LAST_BOARD);
}
}
faV3Inited = nfaV3;
if(nfaV3 <= 0)
{
printf("%s: ERROR: No FADCs initialized\n", __func__);
return (ERROR);
}
printf("%s: %d FADC(s) successfully initialized\n",
__func__, nfaV3);
return nfaV3;
} //End of faInit
int32_t
faV3CheckAddresses()
{
faV3_t baseregs;
u_long offset = 0, expected = 0, base = 0;
faV3_t *v3p = (faV3_t *) &baseregs;
base = (u_long) v3p;
offset = ((u_long) &v3p->adc.status0) - base;
expected = 0x100;
if(offset != expected)
printf("%s: ERROR: status0 not at expected offset 0x%lx (@ 0x%lx)\n",
__func__,expected,offset);
offset = ((u_long) &v3p->adc.config6) - base;
expected = 0x136;
if(offset != expected)
printf("%s: ERROR: adc.config6 not at expected offset 0x%lx (@ 0x%lx)\n",
__func__,expected,offset);
offset = ((u_long) &v3p->adc.rogue_ptw_fall_back) - base;
expected = 0x162;
if(offset != expected)
printf("%s: ERROR: adc.rogue_ptw_fall_back not at expected offset 0x%lx (@ 0x%lx)\n",
__func__,expected,offset);
offset = ((u_long) &v3p->adc.la_dat[0]) - base;
expected = 0x210;
if(offset != expected)
printf("%s: ERROR: adc.la_dat[0] not at expected offset 0x%lx (@ 0x%lx)\n",
__func__,expected,offset);
offset = ((u_long) &v3p->scalers.scaler[0]) - base;
expected = 0x300;
if(offset != expected)
printf("%s: ERROR: scalers.scaler[0] not at expected offset 0x%lx (@ 0x%lx)\n",
__func__,expected,offset);
offset = ((u_long) &v3p->system_test.testbit) - base;
expected = 0x400;
if(offset != expected)
printf("%s: ERROR: system_test.testbit not at expected offset 0x%lx (@ 0x%lx)\n",
__func__,expected,offset);
offset = ((u_long) &v3p->aux.state_level) - base;
expected = 0x500;
if(offset != expected)
printf("%s: ERROR: aux.state_level not at expected offset 0x%lx (@ 0x%lx)\n",
__func__,expected,offset);
return 0;
}
void
faV3SetA32BaseAddress(uint32_t addr)
{
faV3A32Base = addr;
printf("fadc A32 base address set to 0x%08X\n", faV3A32Base);
}
/**
* @ingroup Status
* @brief Convert an index into a slot number, where the index is
* the element of an array of FADCs in the order in which they were
* initialized.
*
* @param[in] i Initialization number
* @return Slot number if Successfull, otherwise ERROR.
*
*/
int
faV3Slot(uint32_t i)
{
if(i >= nfaV3)
{
printf("%s: ERROR: Index (%d) >= FADCs initialized (%d).\n",
__func__, i, nfaV3);
return ERROR;
}
return faV3ID[i];
}
/**
* @ingroup Status
* @brief Convert a slot number into the index, where the index is
* the element of an array of FADCs in the order in which they were
* initialized.
*
* @param[in] slot faV3 slot number
* @return Index if Successfull, otherwise ERROR.
*
*/
int
faV3Id(uint32_t slot)
{
int id;
for(id = 0; id < nfaV3; id++)
{
if(faV3ID[id] == slot)
{
return (id);
}
}
printf("%s: ERROR: FADC in slot %d does not exist or not initialized.\n",
__func__, slot);
return (ERROR);
}
int
faV3GetN()
{
return (nfaV3);
}
/**
* @ingroup Config
* @brief Set the clock source
*
* This routine should be used in the case that the source clock
* is NOT set in faInit (and defaults to Internal). Such is the case
* when clocks are synchronized in a many crate system. The clock source
* of the FADC should ONLY be set AFTER those clocks have been set and
* synchronized.
*
* @param id Slot Number
* @param clkSrc 2 bit integer
* <pre>
* bits 1-0: defines Clock Source
* 0 0 Internal 250MHz Clock
* 0 1 Front Panel
* 1 0 VXS (P0)
* 1 1 VXS (P0)
* </pre>
*
* @return OK if successful, otherwise ERROR.
*/
int
faV3SetClockSource(int id, int clkSrc)
{
CHECKID;
if(clkSrc > 0x3)
{
printf("%s: ERROR: Invalid Clock Source specified (0x%x)\n",
__func__, clkSrc);
return ERROR;
}
/* Enable Clock source - Internal Clk enabled by default */
FAV3LOCK;
vmeWrite32(&(FAV3p[id]->ctrl1),
(vmeRead32(&FAV3p[id]->ctrl1) & ~(FAV3_REF_CLK_MASK)) |
(clkSrc | FAV3_ENABLE_INTERNAL_CLK));
taskDelay(20);
FAV3UNLOCK;
switch (clkSrc)
{
case FAV3_REF_CLK_INTERNAL:
printf("%s: FADC id %d clock source set to INTERNAL\n", __func__, id);
break;
case FAV3_REF_CLK_FP:
printf("%s: FADC id %d clock source set to FRONT PANEL\n",
__func__, id);
break;
case FAV3_REF_CLK_P0:
printf("%s: FADC id %d clock source set to VXS (P0)\n", __func__, id);
break;
case FAV3_REF_CLK_MASK:
printf("%s: FADC id %d clock source set to VXS (P0)\n", __func__, id);
break;
}
/* Re-run the idelay configuration */
faV3LoadIdelay(id, 0);
return OK;
}
/**
* @ingroup Config
* @brief Set the clock source for all initialized modules
*
* This routine should be used in the case that the source clock
* is NOT set in faInit (and defaults to Internal). Such is the case
* when clocks are synchronized in a many crate system. The clock source
* of the FADC should ONLY be set AFTER those clocks have been set and
* synchronized.
*
* @param clkSrc 2 bit integer
* <pre>
* bits 1-0: defines Clock Source
* 0 0 Internal 250MHz Clock
* 0 1 Front Panel
* 1 0 VXS (P0)
* 1 1 VXS (P0)
* </pre>
*
* @return OK if successful, otherwise ERROR.
*/
int
faV3GSetClockSource(int clkSrc)
{
int ifa, id;
if(clkSrc > 0x3)
{
printf("%s: ERROR: Invalid Clock Source specified (0x%x)\n",
__func__, clkSrc);
return ERROR;
}
/* Enable Clock source - Internal Clk enabled by default */
FAV3LOCK;
for(ifa = 0; ifa < nfaV3; ifa++)
{
id = faV3Slot(ifa);
vmeWrite32(&(FAV3p[id]->ctrl1),
(vmeRead32(&FAV3p[id]->ctrl1) & ~(FAV3_REF_CLK_MASK)) |
(clkSrc | FAV3_ENABLE_INTERNAL_CLK));
}
taskDelay(20);
FAV3UNLOCK;
switch (clkSrc)
{
case FAV3_REF_CLK_INTERNAL:
printf("%s: FADC clock source set to INTERNAL\n", __func__);
break;