PowerPC condition-code optimization

[SamuraiCrow]

Normally, the blockers to making a 68k program pipeline friendly are condition codes needing to be generated immediately before the branch or extended-precision math function consumes them. To compensate for this, PPC has eight different condition code registers. This allows comparisons to be performed more than one instruction ahead of time. This allows "delay slots" to be implemented in ways that the 68k cannot do.

Since there are so many more condition-code registers than are needed, a round-robin scheduler should be sufficent to rotate between them to avert some problems with branch-laden code.

[SamuraiCrow]

This is an extension of #40 because rearranging instructions is the duty of the pipeline optimizer pass. I'll need to see to it that the relevant filter code from the framework is placed somewhere where all CPUs can inherit from it. That way more specialized forms of it can be developed.

[SamuraiCrow]

Scratch that, I've given both a more generalized issue to track code rearrangement optimizations.

[SamuraiCrow]

After consulting about this with an AI bot, it indicated from its sources that multiple condition code registers could be used to perform multiple comparisons back-to-back and use some bit-masking of the master condition code register (CR) that contains all of them to produce a single branch from all of the comparisons combined. This "one branch to rule them all" technique could be used on loop conditions that have multiple arms of comparison without having to use short-circuit evaluation, which could result in pipeline stalls.