Process Configuration TOML Specification

Overview

This document defines the TOML format for manufacturing process configuration used by both ChipFlow Backend and LibreLane. Process configurations define reusable technology settings including PDK files, pad rings, shell integration, and process-specific constraints.

Key Principle: Process configurations are technology-specific and design-agnostic. They define "how to manufacture" but not "what to manufacture".

Purpose and Scope

What Goes in Process Configuration (TOML)

✅ PDK and Technology Files

Technology LEF, standard cell LEF/GDS/Liberty files
PDK paths and library settings
Process design rules

✅ Manufacturing Process Settings

Standard cell library selection
Process node characteristics (max fanout, routing layers)
Technology-specific tool settings

✅ Pad Ring and Package Configuration

Pad ring type (Caravel, PGA144, QFN, custom)
Available pad definitions and locations
Package-specific constraints

✅ Shell/Harness Integration

Predetermined shell templates (Caravel SoC, Efabless harnesses)
Shell-to-core connectivity
Required interface signals

✅ Process-Specific Constraints

Placement density limits
Routing layer restrictions
Technology-specific cell usage rules

What Does NOT Go in Process Configuration

❌ Design-Specific Settings

Design name
RTL source files (Verilog/VHDL)
Top module name

❌ Design Clocks and Timing

Clock port names
Clock periods (design-dependent)
Design-specific SDC constraints

❌ Design I/O

Actual signal names for a specific design
Design-specific pin assignments

❌ Build Paths

Build directory locations
Design-specific output paths
User workspace paths

These remain in: Command-line arguments, design fixture configs, or design-specific JSON/YAML files.

File Naming Convention

Process configuration files should be named descriptively:

Format: <process>_<variant>.toml

Examples:

sky130_caravel.toml - Sky130 process with Caravel pad ring
sky130_standalone.toml - Sky130 process without pad ring
ihp_sg13g2_pga144.toml - IHP SG13G2 with PGA144 package
gf180_qfn64.toml - GF180 with QFN64 package
asap7_test.toml - ASAP7 process for testing

File Structure

# Meta information (required)
[meta]
format_version = "1.0"
process = "sky130"          # Process node name
variant = "caravel"         # Configuration variant
description = "Sky130 process with Caravel pad ring for Efabless chipIgnite"

# Variable substitutions (optional but recommended)
[substitutions]
# Reusable variable definitions

[substitutions.paths]
pdk_root = "${env:PDK_ROOT}"
pdk_dir = "${pdk_root}/sky130"

# PDK and technology configuration (required)
[pdk]
name = "sky130"
root = "${substitutions.paths.pdk_root}"
std_cell_library = "sky130_fd_sc_hd"

[pdk.std]
# Standard cell library files

[pdk.tech]
# Technology files and constraints

# Silicon configuration (for chip-level builds)
[silicon]
pad_ring = "caravel"        # Pad ring type

[silicon.pads]
# Pad definitions for this process/package

[silicon.shell]
# Shell/harness integration (optional)

# Process-specific synthesis settings
[synth]
# Technology-specific synthesis constraints

[synth.cells]
# Cell usage rules for this process

# Process-specific PNR settings
[pnr]
# Placement and routing constraints for this process

[pnr.placer]
# Process-specific placement settings

# Tool configuration
[tools]
# Tool-specific settings for this process

Section Specifications

`[meta]` - Metadata (Required)

Process configuration metadata.

Key	Type	Required	Description
`format_version`	string	Yes	TOML format specification version (current: "1.0")
`process`	string	Yes	Process node name (e.g., "sky130", "gf180", "ihp_sg13g2")
`variant`	string	Yes	Configuration variant (e.g., "caravel", "pga144", "standalone")
`description`	string	No	Human-readable description of this configuration
`maintainer`	string	No	Configuration maintainer contact
`last_updated`	string	No	ISO 8601 date of last update

Example:

[meta]
format_version = "1.0"
process = "sky130"
variant = "caravel"
description = "Sky130 with Caravel pad ring for Efabless chipIgnite"
maintainer = "process-configs@example.com"
last_updated = "2025-01-12"

`[substitutions]` - Variable Definitions (Optional)

Reusable variables for path management and value substitution.

Substitution Syntax:

${var} - Reference to another variable
${section.var} - Reference to variable in specific section
${env:VAR} - Environment variable reference

Common Patterns:

[substitutions.paths]
pdk_root = "${env:PDK_ROOT}"
pdk_dir = "${pdk_root}/${pdk.name}"
scl_dir = "${pdk_dir}/libs.ref/${pdk.std_cell_library}"

[substitutions.files]
tech_lef = "${scl_dir}/techlef/${pdk.std_cell_library}.tlef"

`[pdk]` - PDK Configuration (Required)

Process Design Kit configuration including all technology files.

Key	Type	Required	Description
`name`	string	Yes	PDK name (e.g., "sky130", "gf180mcu")
`root`	string	Yes	PDK root directory path
`std_cell_library`	string	Yes	Standard cell library name

Example:

[pdk]
name = "sky130"
root = "${env:PDK_ROOT}"
std_cell_library = "sky130_fd_sc_hd"

`[pdk.std]` - Standard Cell Library

Standard cell library files and settings.

Key	Type	Description
`liberty`	array[string]	Liberty timing files (multiple corners)
`gds`	array[string]	GDS layout files
`lef`	string or array	LEF files (physical library)
`site`	string	Standard cell site name (e.g., "unithd")
`vdd_pin`	string	Power pin name (default: "VPWR")
`gnd_pin`	string	Ground pin name (default: "VGND")
`vdd_voltage`	float	Power supply voltage in volts

Example:

[pdk.std]
liberty = [
    "${substitutions.files.scl_dir}/lib/sky130_fd_sc_hd__tt_025C_1v80.lib",
    "${substitutions.files.scl_dir}/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib",
    "${substitutions.files.scl_dir}/lib/sky130_fd_sc_hd__ss_100C_1v60.lib",
]
gds = ["${substitutions.files.scl_dir}/gds/sky130_fd_sc_hd.gds"]
lef = ["${substitutions.files.scl_dir}/lef/sky130_fd_sc_hd.lef"]
site = "unithd"
vdd_pin = "VPWR"
gnd_pin = "VGND"
vdd_voltage = 1.8

`[pdk.tech]` - Technology Configuration

Technology files and process constraints.

Key	Type	Description
`tech_lef`	string	Technology LEF file
`max_fanout`	integer	Maximum fanout constraint
`ir_drop_layer`	string	Layer for IR drop analysis
`min_routing_layer`	string	Minimum routing layer
`max_routing_layer`	string	Maximum routing layer
`min_clk_routing_layer`	string	Minimum clock routing layer

Example:

[pdk.tech]
tech_lef = "${substitutions.files.tech_lef}"
max_fanout = 32
ir_drop_layer = "met1"
min_routing_layer = "met1"
max_routing_layer = "met5"
min_clk_routing_layer = "met3"

`[pdk.io]` - I/O Pad Library (Optional)

I/O pad library files for chip-level builds.

Key	Type	Description
`pads_lef`	string	I/O pads LEF file
`pads_gds`	string	I/O pads GDS file
`pads_liberty`	string	I/O pads Liberty file

Example:

[pdk.io]
pads_lef = "${pdk.root}/${pdk.name}/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef"
pads_gds = "${pdk.root}/${pdk.name}/libs.ref/sky130_fd_io/gds/sky130_fd_io.gds"
pads_liberty = "${pdk.root}/${pdk.name}/libs.ref/sky130_fd_io/lib/sky130_fd_io__tt_025C_1v80.lib"

`[pdk.rcx]` - Parasitic Extraction

Parasitic extraction rules for this process.

Key	Type	Description
`rules_file`	string	RC extraction rules file

`[silicon]` - Silicon Configuration (Optional)

Silicon-level settings for chip builds with pad rings.

Key	Type	Required	Description
`pad_ring`	string	No	Pad ring type ("caravel", "pga144", "qfn64", "custom", "none")

`[silicon.pads]` - Pad Definitions

Available pads for this process/package. Design-specific pad assignments reference these.

Format: Inline table with type and loc keys.

Pad Types:

"clk" - Clock pad
"i" - Input pad
"o" - Output pad
"io" - Bidirectional pad
"power" - Power pad
"ground" - Ground pad
"analog" - Analog pad

Example:

[silicon.pads]
# Caravel mprj_io pads (available locations)
mprj_io_0 = { type = "io", loc = "0", description = "GPIO 0" }
mprj_io_1 = { type = "io", loc = "1", description = "GPIO 1" }
mprj_io_2 = { type = "io", loc = "2", description = "GPIO 2" }
# ... more pads

# Or PGA144 package:
pad_a1 = { type = "io", loc = "A1", bank = "1" }
pad_a2 = { type = "io", loc = "A2", bank = "1" }
# ... more pads

`[silicon.shell]` - Shell/Harness Integration (Optional)

Configuration for predetermined shells (Caravel, Efabless harnesses).

Key	Type	Description
`template`	string	Shell template name
`core_wrapper`	string	Core wrapper module name
`required_signals`	array[string]	Required interface signals from design

Example:

[silicon.shell]
template = "caravel_user_project"
core_wrapper = "user_project_wrapper"
required_signals = ["wb_clk_i", "wb_rst_i", "wbs_stb_i", "wbs_cyc_i", "wbs_we_i"]

[silicon.shell.connections]
# Shell signal → Core signal mappings (if needed)
wb_clk_i = "clk"
wb_rst_i = "rst_n"

`[synth]` - Synthesis Configuration

Process-specific synthesis settings.

Key	Type	Description
`flatten`	boolean	Flatten hierarchy during synthesis
`no_timing`	boolean	Disable timing-driven synthesis

`[synth.abc]` - ABC Synthesis Settings

ABC synthesis parameters for this process.

Key	Type	Description
`area`	integer	Area optimization (0=off, 1=on)
`driver_cell`	string	Default driver cell
`load`	float	Load capacitance in femtofarads

Example:

[synth.abc]
area = 1
driver_cell = "sky130_fd_sc_hd__buf_1"
load = 5.0

`[synth.cells]` - Cell Constraints

Cell usage rules for this process.

Key	Type	Description
`dont_use`	array[string]	Cells to exclude from synthesis
`fill`	array[string]	Fill/decap cell patterns
`tiehi`	string	Tie-high cell name
`tielo`	string	Tie-low cell name
`min_buf`	string	Minimum buffer cell
`tap`	string	Substrate/well tap cell
`clk_buf`	string	Clock buffer cell
`clk_gate`	string	Clock gate cell

Example:

[synth.cells]
dont_use = [
    "sky130_fd_sc_hd__probe_p_8",
    "sky130_fd_sc_hd__probec_p_8",
    "sky130_fd_sc_hd__lpflow_*",  # Wildcard pattern
]
fill = [
    "sky130_fd_sc_hd__decap_3",
    "sky130_fd_sc_hd__fill_1",
    "sky130_fd_sc_hd__fill_2",
    "sky130_fd_sc_hd__fill_4",
    "sky130_fd_sc_hd__fill_8",
]
tiehi = "sky130_fd_sc_hd__conb_1"
tielo = "sky130_fd_sc_hd__conb_1"
min_buf = "sky130_fd_sc_hd__buf_4"
tap = "sky130_fd_sc_hd__tapvpwrvgnd_1"
clk_buf = "sky130_fd_sc_hd__clkbuf_4"
clk_gate = "sky130_fd_sc_hd__dlclkp_1"

`[synth.map]` - Technology Mapping

Technology-specific mapping files.

Key	Type	Description
`latch`	string	Latch mapping file path
`clkgate`	string	Clock gate mapping file path
`adder`	string	Adder mapping file path

Example:

[synth.map]
latch = "${substitutions.paths.plugin_dir}/verilog/cells_latch.v"
clkgate = "${substitutions.paths.plugin_dir}/verilog/cells_clkgate.v"
adder = "${substitutions.paths.plugin_dir}/verilog/cells_adder.v"

`[pnr]` - Place and Route Configuration

Process-specific PNR settings.

Key	Type	Description
`min_routing_layer`	string	Minimum routing layer (can override pdk.tech)
`max_routing_layer`	string	Maximum routing layer
`min_clk_routing_layer`	string	Minimum clock routing layer
`remove_abc_buffers`	boolean	Remove ABC-inserted buffers
`match_cell_footprint`	boolean	Match cell footprints during optimization

`[pnr.placer]` - Placement Configuration

Process-specific placement settings.

Key	Type	Description
`density`	float	Target placement density (0.0-1.0)
`macro_halo`	array[float]	Macro halo [x, y] in microns
`io_hlayer`	string	Horizontal I/O layer
`io_vlayer`	string	Vertical I/O layer

Example:

[pnr.placer]
density = 0.4
macro_halo = [40.0, 40.0]
io_hlayer = "met3"
io_vlayer = "met2"

`[tools]` - Tool Configuration (Optional)

Tool-specific settings for this process.

`[tools.klayout]` - KLayout Configuration

Key	Type	Description
`tech_file`	string	KLayout technology file (.lyt)
`layers_file`	string	KLayout layer properties (.lyp)

Example:

[tools.klayout]
tech_file = "${substitutions.paths.objects_dir}/klayout/sky130hd.lyt"
layers_file = "${substitutions.paths.objects_dir}/klayout/sky130hd.lyp"

Complete Examples

Example 1: Sky130 with Caravel Pad Ring

File: sky130_caravel.toml

[meta]
format_version = "1.0"
process = "sky130"
variant = "caravel"
description = "Sky130 HD cells with Caravel pad ring for Efabless chipIgnite"

[substitutions.paths]
pdk_root = "${env:PDK_ROOT}"
pdk_dir = "${pdk_root}/sky130"
std_dir = "${pdk_dir}/libs.ref/sky130_fd_sc_hd"

[pdk]
name = "sky130"
root = "${substitutions.paths.pdk_root}"
std_cell_library = "sky130_fd_sc_hd"

[pdk.std]
liberty = [
    "${substitutions.paths.std_dir}/lib/sky130_fd_sc_hd__tt_025C_1v80.lib",
]
gds = ["${substitutions.paths.std_dir}/gds/sky130_fd_sc_hd.gds"]
lef = ["${substitutions.paths.std_dir}/lef/sky130_fd_sc_hd_merged.lef"]
site = "unithd"
vdd_pin = "VPWR"
gnd_pin = "VGND"
vdd_voltage = 1.8

[pdk.tech]
tech_lef = "${substitutions.paths.std_dir}/techlef/sky130_fd_sc_hd.tlef"
max_fanout = 32
ir_drop_layer = "met1"
min_routing_layer = "met1"
max_routing_layer = "met5"
min_clk_routing_layer = "met3"

[pdk.io]
pads_lef = "${pdk.root}/${pdk.name}/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef"
pads_gds = "${pdk.root}/${pdk.name}/libs.ref/sky130_fd_io/gds/sky130_fd_io.gds"

[silicon]
pad_ring = "caravel"

[silicon.pads]
# Caravel mprj_io pads (GPIO pins available to user project)
mprj_io_0 = { type = "io", loc = "0" }
mprj_io_1 = { type = "io", loc = "1" }
mprj_io_2 = { type = "io", loc = "2" }
mprj_io_3 = { type = "io", loc = "3" }
mprj_io_4 = { type = "io", loc = "4" }
mprj_io_5 = { type = "io", loc = "5" }
# ... (would include all 38 mprj_io pads)

[silicon.shell]
template = "caravel_user_project"
core_wrapper = "user_project_wrapper"
required_signals = ["wb_clk_i", "wb_rst_i"]

[synth.abc]
area = 1
driver_cell = "sky130_fd_sc_hd__buf_1"
load = 5.0

[synth.cells]
dont_use = [
    "sky130_fd_sc_hd__probe_p_8",
    "sky130_fd_sc_hd__probec_p_8",
    "sky130_fd_sc_hd__lpflow_*",
]
fill = [
    "sky130_fd_sc_hd__decap_3",
    "sky130_fd_sc_hd__fill_*",
]
tiehi = "sky130_fd_sc_hd__conb_1"
tielo = "sky130_fd_sc_hd__conb_1"
min_buf = "sky130_fd_sc_hd__buf_4"
tap = "sky130_fd_sc_hd__tapvpwrvgnd_1"

[pnr.placer]
density = 0.4
macro_halo = [40.0, 40.0]
io_hlayer = "met3"
io_vlayer = "met2"

Example 2: IHP SG13G2 with PGA144 Package

File: ihp_sg13g2_pga144.toml

[meta]
format_version = "1.0"
process = "ihp_sg13g2"
variant = "pga144"
description = "IHP SG13G2 BiCMOS process with PGA144 package"

[substitutions.paths]
pdk_root = "${env:PDK_ROOT}"
pdk_dir = "${pdk_root}/ihpsg13g2"

[pdk]
name = "ihp_sg13g2"
root = "${substitutions.paths.pdk_root}"
std_cell_library = "sg13g2_stdcell"

[pdk.std]
liberty = ["${substitutions.paths.pdk_dir}/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib"]
gds = ["${substitutions.paths.pdk_dir}/libs.ref/sg13g2_stdcell/gds/sg13g2_stdcell.gds"]
lef = ["${substitutions.paths.pdk_dir}/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef"]
site = "CoreSite"

[pdk.tech]
tech_lef = "${substitutions.paths.pdk_dir}/libs.tech/lef/sg13g2.tlef"
max_fanout = 20
min_routing_layer = "Metal1"
max_routing_layer = "Metal5"

[silicon]
pad_ring = "pga144"

[silicon.pads]
# PGA144 package pad locations
pad_a1 = { type = "io", loc = "A1", bank = "1" }
pad_a2 = { type = "io", loc = "A2", bank = "1" }
# ... (would include all 144 pad locations)

[synth.cells]
tiehi = "sg13g2_tiehi"
tielo = "sg13g2_tielo"
min_buf = "sg13g2_buf_4"
fill = ["sg13g2_fill_*"]

[pnr.placer]
density = 0.5

Usage

In ChipFlow Backend

Process configurations are loaded by techno plugins during plugin_init():

def plugin_init(cfg):
    # Load process configuration
    process_config = os.path.join(plugin_dir, "config", "sky130_caravel.toml")
    cfg.load(process_config)

    # Design-specific overrides come from command-line or fixture

In LibreLane

Process configurations are loaded separately from design configs:

from librelane.config import load_process_config, Config

# Load process configuration
process_cfg = load_process_config("sky130_caravel.toml")

# Load design configuration
design_cfg = Config.load("design_config.yaml", design_dir=".")

# Merge configs (process settings + design specifics)
final_cfg = merge_configs(process_cfg, design_cfg)

Command-Line Usage

# ChipFlow Backend
chipflow-backend --process-config sky130_caravel.toml design.file=rtlil.il

# LibreLane
librelane --process-config sky130_caravel.toml --design-config mydesign.yaml

Migration from JSON

Converting Techno Plugin Configs

Before (sky130hd.json):

{
  "top": {
    "pdk": {
      "tech_lef": "${pdk_dir}/tech_lef/sky130_fd_sc_hd.tlef",
      "max_fanout": 32
    }
  }
}

After (sky130_standalone.toml):

[meta]
format_version = "1.0"
process = "sky130"
variant = "standalone"

[pdk.tech]
tech_lef = "${pdk_dir}/tech_lef/sky130_fd_sc_hd.tlef"
max_fanout = 32

Key Changes:

Add [meta] section with process/variant
Remove "top" wrapper
Convert $ENV{VAR} → ${env:VAR}
Convert $JSON{path} → ${file:path}
Use TOML tables instead of nested JSON

FilesExpand file tree

PROCESS_CONFIG_SPECIFICATION.md

Latest commit

History

PROCESS_CONFIG_SPECIFICATION.md

File metadata and controls

Process Configuration TOML Specification

Overview

Purpose and Scope

What Goes in Process Configuration (TOML)

What Does NOT Go in Process Configuration

File Naming Convention

File Structure

Section Specifications

[meta] - Metadata (Required)

[substitutions] - Variable Definitions (Optional)

[pdk] - PDK Configuration (Required)

[pdk.std] - Standard Cell Library

[pdk.tech] - Technology Configuration

[pdk.io] - I/O Pad Library (Optional)

[pdk.rcx] - Parasitic Extraction

[silicon] - Silicon Configuration (Optional)

[silicon.pads] - Pad Definitions

[silicon.shell] - Shell/Harness Integration (Optional)

[synth] - Synthesis Configuration

[synth.abc] - ABC Synthesis Settings

[synth.cells] - Cell Constraints

[synth.map] - Technology Mapping

[pnr] - Place and Route Configuration

[pnr.placer] - Placement Configuration

[tools] - Tool Configuration (Optional)

[tools.klayout] - KLayout Configuration

Complete Examples

Example 1: Sky130 with Caravel Pad Ring

Example 2: IHP SG13G2 with PGA144 Package

Usage

In ChipFlow Backend

In LibreLane

Command-Line Usage

Migration from JSON

Converting Techno Plugin Configs

Validation

Required Sections

Optional but Recommended

See Also

`[meta]` - Metadata (Required)

`[substitutions]` - Variable Definitions (Optional)

`[pdk]` - PDK Configuration (Required)

`[pdk.std]` - Standard Cell Library

`[pdk.tech]` - Technology Configuration

`[pdk.io]` - I/O Pad Library (Optional)

`[pdk.rcx]` - Parasitic Extraction

`[silicon]` - Silicon Configuration (Optional)

`[silicon.pads]` - Pad Definitions

`[silicon.shell]` - Shell/Harness Integration (Optional)

`[synth]` - Synthesis Configuration

`[synth.abc]` - ABC Synthesis Settings

`[synth.cells]` - Cell Constraints

`[synth.map]` - Technology Mapping

`[pnr]` - Place and Route Configuration

`[pnr.placer]` - Placement Configuration

`[tools]` - Tool Configuration (Optional)

`[tools.klayout]` - KLayout Configuration