clk_gen_usp: The frequency of internally generated clocks is inaccurate.

[walliv]

The computation of the frequency of internal clock cannot be done in a general way by only putting the frequency of input clock as generic parameter. The MMCM needs to be driven directly by its frequency dividers/multipliers. This proposes the use of a 3-element vector that contains numbers M,D and O, that is (M,D,O). These values are then computed using the formula in UG572 to output an exact frequency on the MMCM outputs. The MMCM version should also be chosen according to the used architecture, that is MMCM4 for UltraScale+ architecture.

[jakubcabal]

Yes, there is room for improvement. However, it would be advisable to design the clock generation configuration so that it can also be used on the Intel FPGA PLL. In the case of Intel FPGAs, the parameters are now set manually in the Quartus GUI and the corresponding .ip file is subsequently generated.