@@ -61,9 +61,15 @@ const Double_t V3Layer::sIBFPCAlAnodeWidth1 = 13.0 * sMm;
6161const Double_t V3Layer::sIBFPCAlAnodeWidth2 = 14.7 * sMm ;
6262const Double_t V3Layer::sIBFlexCableKapThick = 75.0 * sMicron ;
6363const Double_t V3Layer::sIBFlexCablePolyThick = 20.0 * sMicron ;
64- const Double_t V3Layer::sIBFlexCapacitorXWid = 0.2 * sMm ;
65- const Double_t V3Layer::sIBFlexCapacitorYHi = 0.2 * sMm ;
66- const Double_t V3Layer::sIBFlexCapacitorZLen = 0.4 * sMm ;
64+ const Double_t V3Layer::sIBFlexCapacitor1XWid = 0.5 * sMm ;
65+ const Double_t V3Layer::sIBFlexCapacitor1YHi = 0.5 * sMm ;
66+ const Double_t V3Layer::sIBFlexCapacitor1ZLen = 1.0 * sMm ;
67+ const Double_t V3Layer::sIBFlexCapacitor22XWid = 0.7 * sMm ;
68+ const Double_t V3Layer::sIBFlexCapacitor22YHi = 0.6 * sMm ;
69+ const Double_t V3Layer::sIBFlexCapacitor22ZLen = 1.1 * sMm ;
70+ const Double_t V3Layer::sIBFlexResistorXWid = 0.2 * sMm ;
71+ const Double_t V3Layer::sIBFlexResistorYHi = 0.2 * sMm ;
72+ const Double_t V3Layer::sIBFlexResistorZLen = 0.4 * sMm ;
6773const Double_t V3Layer::sIBColdPlateWidth = 15.4 * sMm ;
6874const Double_t V3Layer::sIBColdPlateZLen = 290.0 * sMm ;
6975const Double_t V3Layer::sIBGlueThick = 50.0 * sMicron ;
@@ -599,8 +605,11 @@ TGeoVolume* V3Layer::createModuleInnerB(const Double_t xchip, const Double_t zch
599605 // the module as a TGeoVolume
600606 //
601607 // Updated: 03 Apr 2021
608+ // Updated: 03 Nov 2025 Change volume from BBox to Xtru to avoid fake overlaps
602609
603610 Double_t xtot, ytot, ztot;
611+ Double_t ymid, shrinkFactor = 0.73 ;
612+ Double_t xv[5 ], yv[5 ];
604613 Double_t xpos, ypos, zpos;
605614 const Int_t nameLen = 30 ;
606615 char volumeName[nameLen];
@@ -619,9 +628,25 @@ TGeoVolume* V3Layer::createModuleInnerB(const Double_t xchip, const Double_t zch
619628 Double_t ygnd = (static_cast <TGeoBBox*>(aluGndCableVol->GetShape ()))->GetDY ();
620629 Double_t yano = (static_cast <TGeoBBox*>(aluAnodeCableVol->GetShape ()))->GetDY ();
621630
622- ytot = sIBGlueThick / 2 + ygnd + sIBFlexCableKapThick / 2 + yano + sIBFlexCapacitorYHi / 2 ;
631+ ytot = sIBGlueThick / 2 + ygnd + sIBFlexCableKapThick / 2 + yano + sIBFlexCapacitor22YHi / 2 ;
632+ ymid = sIBGlueThick / 2 + ygnd + sIBFlexCableKapThick / 2 + yano;
623633
624- TGeoBBox* module = new TGeoBBox (xtot, ytot, ztot);
634+ xv[0 ] = xtot;
635+ yv[0 ] = -ytot;
636+ xv[1 ] = xv[0 ];
637+ yv[1 ] = yv[0 ] + 6 * ymid;
638+ xv[2 ] = xtot * shrinkFactor;
639+ yv[2 ] = ytot;
640+ xv[3 ] = -xtot;
641+ yv[3 ] = yv[2 ];
642+ xv[4 ] = xv[3 ];
643+ yv[4 ] = yv[0 ];
644+
645+ TGeoXtru* module = new TGeoXtru (2 );
646+ module ->DefinePolygon (6 , xv, yv);
647+ module ->DefinePolygon (5 , xv, yv);
648+ module ->DefineSection (0 , -ztot);
649+ module ->DefineSection (1 , ztot);
625650
626651 // Now the volumes
627652 TGeoMedium* medAir = mgr->GetMedium (Form (" %s_AIR$" , GetDetName ()));
@@ -674,6 +699,7 @@ void V3Layer::createIBCapacitors(TGeoVolume* modvol, Double_t zchip, Double_t yz
674699 //
675700 // Created: 13 Feb 2018 Mario Sitta
676701 // Updated: 03 Apr 2019 Mario Sitta Fix positions (180' rotation)
702+ // Updated: 31 Oct 2025 Mario Sitta Fix dimensions and weight
677703 //
678704
679705 // Position of the various capacitors (A.Junique private communication
@@ -705,63 +731,72 @@ void V3Layer::createIBCapacitors(TGeoVolume* modvol, Double_t zchip, Double_t yz
705731 Double_t xpos, ypos, zpos;
706732 Int_t nCapacitors;
707733
708- TGeoVolume *capacitor , *resistor;
734+ TGeoVolume *capacitorSmall, *capacitorLarge , *resistor;
709735
710- // Check whether we already have the volume , otherwise create it
711- // (so as to avoid creating multiple copies of the very same volume
736+ // Check whether we already have the volumes , otherwise create them
737+ // (so as to avoid creating multiple copies of the very same volumes
712738 // for each layer)
713- capacitor = mgr->GetVolume (" IBFPCCapacitor" );
739+ // The "small" capacitor is the 1 uF substrate capacitor
740+ // The "large" capacitor is the 22 uF analog/digital PS capacitor
741+ capacitorSmall = mgr->GetVolume (" IBFPCCapacitorSmall" );
714742
715- if (!capacitor) {
716- TGeoBBox* capsh = new TGeoBBox (sIBFlexCapacitorXWid / 2 , sIBFlexCapacitorYHi / 2 , sIBFlexCapacitorZLen / 2 );
743+ if (!capacitorSmall) {
744+ TGeoBBox* capSmsh = new TGeoBBox (sIBFlexCapacitor1XWid / 2 , sIBFlexCapacitor1YHi / 2 , sIBFlexCapacitor1ZLen / 2 );
745+ TGeoBBox* capLgsh = new TGeoBBox (sIBFlexCapacitor22XWid / 2 , sIBFlexCapacitor22YHi / 2 , sIBFlexCapacitor22ZLen / 2 );
717746
718747 TGeoMedium* medCeramic = mgr->GetMedium (Form (" %s_CERAMIC$" , GetDetName ()));
719748
720- capacitor = new TGeoVolume (" IBFPCCapacitor" , capsh, medCeramic);
721- capacitor->SetLineColor (kBlack );
722- capacitor->SetFillColor (kBlack );
749+ capacitorSmall = new TGeoVolume (" IBFPCCapacitorSmall" , capSmsh, medCeramic);
750+ capacitorSmall->SetLineColor (kBlack );
751+ capacitorSmall->SetFillColor (kBlack );
752+
753+ capacitorLarge = new TGeoVolume (" IBFPCCapacitorLarge" , capLgsh, medCeramic);
754+ capacitorLarge->SetLineColor (kBlack );
755+ capacitorLarge->SetFillColor (kBlack );
723756
724- TGeoBBox* ressh = new TGeoBBox (sIBFlexCapacitorXWid / 2 , // Resistors have
725- sIBFlexCapacitorYHi / 2 , // the same dim's
726- sIBFlexCapacitorZLen / 2 ); // as capacitors
757+ TGeoBBox* ressh = new TGeoBBox (sIBFlexResistorXWid / 2 ,
758+ sIBFlexResistorYHi / 2 ,
759+ sIBFlexResistorZLen / 2 );
727760
728761 resistor = new TGeoVolume (" IBFPCResistor" , ressh, medCeramic);
729762 resistor->SetLineColor (kBlack );
730763 resistor->SetFillColor (kBlack );
731764 } else { // Volumes already defined, get them
765+ capacitorLarge = mgr->GetVolume (" IBFPCCapacitorLarge" );
732766 resistor = mgr->GetVolume (" IBFPCResistor" );
733767 }
734768
735769 // Place all the capacitors (they are really a lot...)
736- ypos = yzero + sIBFlexCapacitorYHi / 2 ;
770+ ypos = yzero + sIBFlexCapacitor22YHi / 2 ;
737771
738772 xpos = xGroup1A;
739773 for (Int_t j = 0 ; j < sIBChipsPerRow ; j++) {
740774 zpos = -mIBModuleZLength / 2 + j * (2 * zchip + sIBChipZGap ) + zchip + zGroup1A[0 ];
741- modvol->AddNode (capacitor , 2 * j + 1 , new TGeoTranslation (-xpos, ypos, -zpos));
775+ modvol->AddNode (capacitorLarge , 2 * j + 1 , new TGeoTranslation (-xpos, ypos, -zpos));
742776 zpos = -mIBModuleZLength / 2 + j * (2 * zchip + sIBChipZGap ) + zchip + zGroup1A[1 ];
743- modvol->AddNode (capacitor , 2 * j + 2 , new TGeoTranslation (-xpos, ypos, -zpos));
777+ modvol->AddNode (capacitorLarge , 2 * j + 2 , new TGeoTranslation (-xpos, ypos, -zpos));
744778 }
745779
746780 nCapacitors = 2 * sIBChipsPerRow ;
747781 xpos = xGroup1B;
748782 for (Int_t j = 0 ; j < sIBChipsPerRow ; j++) {
749783 zpos = -mIBModuleZLength / 2 + j * (2 * zchip + sIBChipZGap ) + zchip + zGroup1B;
750- modvol->AddNode (capacitor , j + 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
784+ modvol->AddNode (capacitorLarge , j + 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
751785 }
752786
753787 nCapacitors += sIBChipsPerRow ;
788+ ypos = yzero + sIBFlexCapacitor1YHi / 2 ;
754789 xpos = xGroup2;
755790 // We have only 8 in these group, missing the central one
756791 for (Int_t j = 0 ; j < sIBChipsPerRow - 1 ; j++) {
757792 zpos = -mIBModuleZLength / 2 + j * (2 * zchip + sIBChipZGap ) + zchip + zGroup2;
758- modvol->AddNode (capacitor , j + 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
793+ modvol->AddNode (capacitorSmall , j + 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
759794 }
760795
761796 nCapacitors += (sIBChipsPerRow - 1 );
762797 xpos = xGroup3;
763798 zpos = zGroup3;
764- modvol->AddNode (capacitor , 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
799+ modvol->AddNode (capacitorSmall , 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
765800
766801 nCapacitors++;
767802 for (Int_t j = 0 ; j < sIBChipsPerRow ; j++) {
@@ -771,25 +806,26 @@ void V3Layer::createIBCapacitors(TGeoVolume* modvol, Double_t zchip, Double_t yz
771806 xpos = xGroup4[0 ];
772807 }
773808 zpos = -mIBModuleZLength / 2 + j * (2 * zchip + sIBChipZGap ) + zchip + zGroup4[j];
774- modvol->AddNode (capacitor , j + 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
809+ modvol->AddNode (capacitorSmall , j + 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
775810 }
776811
777812 nCapacitors += sIBChipsPerRow ;
813+ ypos = yzero + sIBFlexCapacitor22YHi / 2 ;
778814 for (Int_t j = 0 ; j < nGroup5A; j++) {
779815 if (j == 0 ) {
780816 xpos = xGroup5A[0 ];
781817 } else {
782818 xpos = xGroup5A[1 ];
783819 }
784820 zpos = zGroup5A[j];
785- modvol->AddNode (capacitor , j + 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
821+ modvol->AddNode (capacitorLarge , j + 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
786822 }
787823
788824 nCapacitors += nGroup5A;
789825 xpos = xGroup5B;
790826 for (Int_t j = 0 ; j < nGroup5B; j++) {
791827 zpos = zGroup5B[j];
792- modvol->AddNode (capacitor , j + 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
828+ modvol->AddNode (capacitorLarge , j + 1 + nCapacitors, new TGeoTranslation (-xpos, ypos, -zpos));
793829 }
794830
795831 // Place the resistors
@@ -1061,7 +1097,7 @@ TGeoVolume* V3Layer::createStaveModelInnerB4(const TGeoManager* mgr)
10611097 yv[1 ] = layerHeight + sIBSideVertexHeight + topfil->GetDZ ();
10621098 ;
10631099 xv[2 ] = sIBEndSupportXUp / 2 ;
1064- yv[2 ] = sIBStaveHeight + sIBTopFilamentSide / sinD (-theta); // theta is neg
1100+ yv[2 ] = sIBStaveHeight + sIBTopFilamentSide / sinD (-theta) - 0.01 ; // theta is neg
10651101 for (Int_t i = 0 ; i < 3 ; i++) {
10661102 xv[3 + i] = -xv[2 - i];
10671103 yv[3 + i] = yv[2 - i];
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